As semiconductor integrated circuits evolve towards higher speed and greater integration, metal wires have recently been made with finer multilayer structure. Copper and low k (dielectric constant) materials have been introduced to reduce RC signal delay.
Metal patterning in accordance with size reductions within design rules creates difficulties in the manufacturing processes. A dual damascene process for forming wires has been developed which removes a metal etching step and an insulator gap charging step.
In the dual damascene process, a dual damascene pattern is formed over an interlayer dielectric film, allowing conductive material to be buried in a dual damascene pattern, thereby simultaneously forming a contact plug and a metal wire. To form a seed layer of the metal wire, an atomic layer deposition (ALD) process has been used. The ALD process is capable of forming a thin film having excellent step coverage and relatively uniform composition at relatively low temperatures. However, when forming the seed layer in the ALD process, the undesirable by-products carbon (C) and chlorine (Cl) may be produced. Also, when burying the metal wire in an electro chemical plating (ECP) process, voids may be generated, causing deterioration of the electrical properties of the device and device failure.